Layout Engineers·         

Advanced understanding of Deep submicron effects and mitigation, Good exposure on Cadence and Mentor   Graphics tools.

Good understanding of CMOS layouts and process technology in 28nm and below technologies. Hand on experience in FinFet Technology will be added advantage.

Good understanding of ASIC physical design flow: LEF generation, Place & Route.

Good understanding standard cell abutment rules, memory & IO layout design and requirements, EM and IR considerations, DFM, etc.

Scripting skills for layout automation is advantage.

Excellent written and verbal communication skills in interactions with customers, and internal development   teams.

We focus on hiring only the best talent in the industry. As a member of our fast growing team, you are valued for your efforts and your career growth is driven entirely by your performance. We have following openings at Bangalore. If you are interested, please send your updated Resume to


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Senior/Lead Verification Engineers
Job description:
Responsible for Functional/Netlist Verification of complex ASIC/SoCs
Create a Testplan and Coverage plan
Develop Test bench including TB Components, functional coverage model, environment and Testcases and verify the functionality at for Block and Chip level
Job Requirements:

3-8 Years of Experience in ASIC/SoC Design Verification
Exposure to EDA tools viz. VCS, NC-Sim, Questasim
Good in debugging and problem solving skills
Proficient in System Verilog, SVA and C++ and PERL scripting
Proficient in using verification methodologies like VMM, OVM and UVM
BE/BTECH/ME/MTECH in EC/EE/CS or related field


DFT Engineers
Job Description:
Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at-speed testing, I/O testing requirements, MBIST and Repair, Implement Test Logic.
Generate and debug test patterns
Job Requirements:
3-8 Years of Experience in DFT
BE/BTECH/ME/MTECH in EC/EE/CS or related field
Exposure to EDA tools viz. DC, LogicVision, Fastscan, Tetramax
Good knowledge about all DFT concepts & ATPG Flow.
Vector Generation, ATPG Pattern Generation, Validation, Scan insertion and validation, Timing Analysis


​​​Physical Design Engineer​Physical Design Engineers
Job Description:
Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.
High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows
Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;
Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and Full Chip Physical Designs
Knowledge of EDA vendor (Synopsys, Cadence, Magma, Mentor, etc.) tools suite like Apollo, Astro,Physical Compiler, PrimeTime, dc_shell, Silicon Ensemble, First Encounter, PKS, Nanoroute, is a plus.
Should be independent, self-driven and a strong team player.
Qualifications: B.Tech / M.Tech or equivalent from a reputed University with 2 - 8 years of relevant experience
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ASIC Design Engineers
Job Description:
Strong in digital design fundamentals
Expertise in micro architecture development, design, RTL Coding & integration of IP blocks in ASIC/SoC designs
Very good understanding of timing requirements, synthesis flows and experience in formal verification flows
Design for test and Design for debug (DFx) is a plus
Very good understanding of system level architecture and validation flows
Highly motivated individuals and ability to deal with ambiguity
Ability to work in a team environment
Good hands-on expertise in Perl, Shell and Unix scripting
Job Requirements:
3-8 Years of Experience in ASIC/SoC Design
BE/BTECH/ME/MTECH in EC/EE/CS or related field
Proven track record of successful ASIC designs from design to production in leading-edge technology