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Lead - Physical Design Engineer
Roles & Responsibilities
  • 7 - 8 years of experience in PnR
  • Have done 2-3 Top level PnR with Timing Closure
  • Lead a team of Engineers
  • Have in-depth knowledge of entire physical design process from RTL to GDS2
    generation
  • which includes floorplan, Placement, CTS, Routing and Sign Off ( STA, PV,
    IR/EM)
  • Have hands-on experience in latest sub-micron technologies below 14nm
  • Familiar with Physical Verification flows (DRC/LVS/EM/IR)
  • Experience in ECO implementation
  • Hands on experience in  PnR tools Synopsys ICC II/ Cadence Encounter etc
  • Familiarity with any of Scripting languages –PERL, TCL
  • Should possess good Leadership Skills
  • Must have good communication & problem-solving skills.
  • Should be with Go-getter attitude
  • Mentor Team Members
  • Bachelor/Master Degree in Electronics Engineering
Job Location: Bangalore
Designation: Lead Physical Design Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 7
Lead - Verification Engineer
Roles & Responsibilities
  • 6 - 8 years of experience in Verification
  • Have done 2-3 Top level SoC verification
  • Lead a team of Engineers
  • Expertise with AXI/AHB/APB protocols
  • Knowledge/Expertise with PCIe/MIPI will be an added advantage
  • Knowledge with processor verification is a plus
  • Extensive knowledge of SystemVerilog and verification methodologies particularly OVM/UVM
  • Strong experience in the implementation of verification infrastructures, test benches, models, assertions 
  • Expertise with development of constrained random tests scenarios
  • Running regression tests and analysis of results including functional coverage
  • Hands on with RTL/Gate Level Simulation
  • Expertise with industry standard tools like VCS/Verdi/NCSim/Questa etc.
  • Scripting skills with PERL/TCL
  • Should possess good Leadership Skills
  • Must have good communication & problem-solving skills.
  • Should be with Go-getter attitude
  • Mentor Team Members
  • Bachelor/Master Degree in Electronics Engineering
Job Location: Bangalore
Designation: Lead Design Verification Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 4
Senior Physical Design Engineer
Roles & Responsibilities
  • 3 to 5 years of experience in PnR
  • Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing
  • Have hands-on experience in latest sub-micron technologies below 20nm
  • Have done good number of Block level PnR with Timing Closure
  • Familiar with Physical Verification flows (DRC/LVS/EM/IR)
  • Experience in ECO implementation
  • Familiarity with any of Scripting languages –PERL, TCL
  • Should be a quick learner and have good attention to detail
  • Must have good communication & problem-solving skills.
Job Location: Bangalore/US
Designation: Senior Physical Design Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 40
Sr. ASIC Verification Engineer
Roles & Responsibilities
  • Expertise with AXI/AHB/APB protocols
  • Knowledge/Expertise with PCIe/MIPI will be an added advantage
  • Knowledge with processor verification is a plus
  • Extensive knowledge of System Verilog and verification methodologies particularly OVM/UVM
  • Strong experience in the implementation of verification infrastructures, test benches, models, assertions
  • Expertise with development of constrained random tests scenarios
  • Running regression tests and analysis of results including functional coverage
  • Hands on with RTL/Gate Level Simulation
  • Expertise with industry standard tools like VCS/Verdi/NCSim/Questa etc.
  • Scripting skills with PERL/TCL
  • With Excellent communication and interpersonal skills
  • Very good team player, self motivated and creative in  problem solving
Job Location: US
Designation: Senior Verification Engineer
Experience: 3+ years to 8 years
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 15
Senior DFT Engineer
Roles & Responsibilities
  • Minimum 3 years of experience in areas of  SOC-DFT Implementation and Integration
  • Hands-on experience and knowledge of  ATPG,  ATPG-DRC clean-up, Pattern
  • Generation, fault models, coverage analysis and improvement
  • Hands-on experience with pattern generation for various fault models, Stuck-At, TDF, PDF, IDDQ
  • Experience with pattern verification, simulation debug, ATE pattern delivery and silicon bring-up
  • Experience with one or more  scan/ATPG solutions with Tessent Scan, FastScan, TestKompress
  • Synopsys DC, DFTC, DFTMAX, Tetramax
  • Experience with pattern verification and debug VCS, Simvision,  NC-verilog, Questa
  • Desired experience with failure diagnostics, silicon debug and interfacing with ATE and test engineers for bring-up
  • Preferred but not required MBIST implementation and experience with MBIST pattern generation and verification
  • Preferred but not required experience with one or more MBIST solutions Tessent
  • BIST, MBIST Architect, SMS
  • Experience with shell scripting, Verilog, Tcl and/or Perl/Python
  • Strongly desired  understanding of IEEE 1149.1, P1500 and Core-Based Testing Standards
  • Desired experience with coverage  improvement and yield improvement
  • Desired experience with test constraint generation and working with STA for test mode timing closures
  • Desired familiarity with DFX concepts
  • With Excellent communication and interpersonal skills
  • Very good team player, self-motivated and creative in  problem solving
Designation: Senior DFT Engineer
Experience: 4+ years
Location: Bangalore/Hyderabad/US
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Front-End RTL Design Automation Engineer
Roles & Responsibilities
  • Well versed in Verilog and SV with good understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and/or gate level verification domain is a must.
  • Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process.
  • Knowledge on low power design and verification methods using UPF is a must.
  • Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend.
  • An expert user of one or more of the following verification tools: NC-Sim*, Modelsim*, VCS, Specman*, Debussy* and/or Verdi*
  • Good automation skills in PERL and/or TCL and/or Shell*. Good communication skills (written and verbal).
Designation: Front End RTL Design Automation Engineer
Experience: 2+ years & above
Location: Bangalore/Hyderabad
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Senior Synthesis/STA Engineer
Roles & Responsibilities
  • Experience level: 5+ Years.
  • Work Experience in Synthesis Constraints development, LINT checks, CDC checks
  • Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure.
  • Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.
  • Chip-level constraint development and constraint validation.
  • Strong knowledge of clock tree synthesis, SI analysis.
  • Strong understanding of ECO cycle .
Designation: Senior  Synthesis/STA Engineer
Experience: 4+ years
Location: Bangalore/Hyderabad/US
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Memory Layout Design Engineer
Roles & Responsibilities
  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler
    context.
  • Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
  • Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
  • Good handle on IR/EM related issues in memory layouts.
  • Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
  • Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
  • Experience & or strong interest in memory compilers developed.
  • Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.
Location: Bangalore
Experience: 3+ Years & Above
Qualification: Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 3
Senior Verification Engineer/ Verification Engineer
Job Description
As a Verification Engineer / Senior Verification Engineer, you will work with a highly innovative and motivated verification development team using state of the art verification technologies to verify the most advanced DRAM products. The verification infrastructure you develop/implement will be used world-wide by multiple teams to verify DRAM products. You will work closely with Micron's various design and verification teams all over the world to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries as needed .
Job Responsibilities
  • Using advanced verification languages (HVL) and techniques to build a cutting-edge verification platform to fully evaluate memory designs at chip or block level on functionality
  • Participating in creating full chip behaviour model that is distributed to Micron’s world-wide external customer’s months before silicon is available
  • Building a verification plan, incorporating directed and random patterns that cover all features
  • Understanding the functionality and timing requirements of the design
  • Understand internal and external datasheets
  • Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design
Job Requirements
  • 4+ years of experience in Verification
  • Solid understanding of Verilog, System Verilog and object-oriented programming
  • Experience in VIP development using UVM (or equivalent) is a must
  • Good debugging and problem-solving skills are a must
  • Experience defining coverage strategy and writing coverage model is a must
  • Experience in simulator tools like Synopsys, Cadence, Mentor Graphics is preferred
  • Experience in scripting language like Shell, Perl, Python is preferred
  • Must possess good communication skills to convey complex technical concepts and ability to work well in a team
  • Previous work experience in DRAM memory related fields is a plus
Location: Hyderabad/US
Designation: Senior Verification Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Analog Layout Design Engineer
Roles & Responsibilities
  • 3+ years of experience in AMS/RF layout-design (7nm)
  • Good Understanding of CMOS Fundamentals, IC-Fabrication & Circuit-basics
  • Good Understanding of Layout-Flow & various Reliability Issues
  • Preferred experience in modules like PLL, Data-Converters & PMIC blocks
  • Good exposure to EDA tools like Virtuoso LE/XL, Assura, PVS, Calibre
  • Preferred experience in Deep Sub-Micron/Finfet / Bi-CMOS technologies
  • Independently execute layout-design of the assigned Analog & Mixed-Signal / RF blocks either at Onsite or Off-shore, which includes floor-planning as per area & top-level, parasitic-aware routing & doing various required physical verifications.
  • Responsible for the on-time delivery of block-level layouts, with acceptable quality
  • Co-ordinate effectively with the customer & team-members, for the successful overall project execution
  • Guide junior team-members in their execution of block-level layouts & review their work
  • Contribute to effective project-management.
Location: Bangalore
Experience: 3+ Years & Above
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Senior STA Engineer
Roles & Responsibilities
  • Familiar and rich experience with SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, formality
  • Solid knowledge at FEINT technologies, i.e. synthesis, formality check, CDC, low-power design flow, and STA analysis
  • Good communication skills.
  • Good English capability on both writing and speaking
  • Good self-learning capability and team-work spirit
  • Backend design knowledge is plus
Keywords:SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, forma lity FEINT Complex,STA, synthesis, timing, ECO, LINT, CDC
Designation: STA Engineer
Location: China/US
Notice Period: Immediate or Maximum 1 Month
Experience: 3+ Years
Number of Positions: 5
Overseas Requirements: Senior DFT Engineer
Roles & Responsibilities
  • BS in EE, MS preferred., with minimal 3 years working experience on DFT
  • Familiar with DFT tools like TestKompress, FastScan, Tetra max, MBISTarchitect, BSDarchitect etc.
  • Should have strong problem-solving skills - Good English hearing, speaking, reading and writing capabilities
  • Good team working spirit
Keywords: Cadence DFT architect ATPG MBIST SCAN
Designation: DFT Engineer
Location: China/US
Notice Period: Immediate or Maximum 1 Month
Experience: 3+ Years
Number of Positions: 5
Overseas Requirements -Senior Physical Design Engineer
Roles & Responsibilities
  • 3 to 5 years of experience in PnR
  • Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing
  • Have hands-on experience in latest sub-micron technologies below 20nm
  • Have done good number of Block level PnR with Timing Closure
  • Familiar with Physical Verification flows (DRC/LVS/EM/IR)
  • Experience in ECO implementation
  • Familiarity with any of Scripting languages –PERL, TCL
  • Should be a quick learner and have good attention to detail
  • Must have good communication & problem-solving skills.
Keywords:SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, forma lity FEINT Complex,STA, synthesis, timing, ECO, LINT, CDC
Designation: Senior Physical Design Engineer
Location: Japan/China/Europe/US
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
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