Test Data
Test Data
Test Data
Projects

SOC implementation of Graphic chip (IP implementation)
Tools used : ICC2, Spyglass, Conformal, CALIBRE, Star RC- XT, PrimeTime, ICV and Redhawk
Technology : 7nm TSMC
Responsibilities :
  • Handled Multi-Voltage IP of 14 Blocks
  • Netlist-to-GDS implementation:
  • Understanding Customer Designs, Data flow diagrams
  • Flow/tool, Library setup
  • Working with RTL Team for UPF
  • Giving constraints feedback to synthesis team for timing closure and optimization at different stages of the flow
  • Floorplaning, Power planning (Low power implementation)
  • Implementing multiple voltage Islands for multiple feedthroughs
  • Placement, Post placement timing/congestion optimization
  • CTS, Clock optimization
  • SI Aware Routing
  • Cleaning up shorts, opens and data ready for STA
  • Static Timining analysis and closure
  • ECO Implementation
  • Physical Verification
  • IR/EM Analysis
  • Final Sign off
  • Writing scripts to automate the recurring tasks/steps
Project Description : Tile with 2 operating frequency and 2 power domain with Level Shifter and Low power implementation with UPF.
SOC implementation of Processor chip (Block implementation)
Tools used : Innovus, Spyglass, Conformal, CALIBRE, Star RC- XT, PrimeTime, ICV and Redhawk
Technology : 10nm
Responsibilities :
Netlist-to-GDS implementation:
  • Understanding Customer Designs, Data flow diagrams
  • Flow/tool, Library setup
  • Working with RTL Team for UPF
  • Giving constraints feedback to synthesis team for timing closure and optimization at different stages of the flow
  • Floorplaning, Power planning (Low power implementation)
  • Implementing multiple voltage Islands for multiple feedthroughs
  • Placement, Post placement timing/congestion optimization
  • CTS, Clock optimization
  • SI Aware Routing
  • Cleaning up shorts, opens and data ready for STA
  • Static Timining analysis and closure
  • ECO Implementation
  • Physical Verification
  • IR/EM Analysis
  • Final Sign off
Project Description : 3.5M instances and 304 macros 1.2 GHZ Frequency
Challenges : Understanding Eco implementation flow with short period of time and fixing DRC and LVS.
Subsystem Implementation
Tools used : Innovus, primetime, caliber, PVS, VOULTS and k- layout
Responsibilities :Implementation of floorplanning, PnR, timing and physical signoff
Project Description :
  • This Subsystem of 9 million gate count with huge subblock within the block with 44k Pins , 6 clocks and 48Macros
  • Encountered challenges in Meeting timing, congestion was the major issue along with timing, signoff was also challenging. Had developed scripts that helped in solving issues
Block Implementation
Tools used : Innovus, primetime, caliber, PVS, VOULTS and k- layout
Technology : 16 nm
Responsibilities :Innovus , primetime, PVS ,voltus caliber and k- layout
Project Description :Implementation of floorplanning, PnR, timing and physical signoff
  • Block of 6 million gate count, 50k Pins , 2 clocks and 51Macros
  • Participated in Floor planning, Place and Route implementation
  • Encountered challenges in Meeting timing, congestion was the major issue along with timing.
  • Worked on Timing Fixes, PV fixes based on PVS tool
  • Have done timing signoff.
Implementation of DDR controller in DDR Sub-system
Tools used : Innovus, CALIBRE, Star RC- XT, PrimeTime
Technology : 7nm TSMC
Responsibilities :Netlist-to-GDS implementation, Physical Verification and Timing closure.
Project Description :Block with Rectilinear shape of 0.95mm2 with 2.8 million instance, 12 memories and 2 ESD clamp cells with a frequency of 866MHz.
Fullchip and block level Synthesis and Timing closure
Tools used : Cadence Genus, Tempus, Conformal
Technology : 16nm / 9 Metal Layers
Responsibilities : 
  • Involved in full block Synthesis/corresponding DFT checks
  • Involved in STA & Timing Optimization of various kinds of paths.
Project Description :
  • Technology / Layers : 16nm / 9 Metal Layers.
  • Gate count : 9 million gate design
  • Macros : 22
  • No. of Clocks : 6 master clocks
  • Frequency : 1.4 GHz
Top level Synthesis and Timing closure
Tools used : Cadence Genus, Tempus, Conformal
Responsibilities :Full chip Synthesis and Timing closure
Project Description :
  • Technology : 16nm
  • STD cell count : 3269809
  • Die size : 13.5mmX13.3mm
  • Macros : 1645
  • Contribution : Test modes/struct modes /modal coverage
  • Freq : scan_shift (25Mhz), scan_cap_dc (50Mhz), scan_cap_ac (half/func_freq), jtag(10 Mhz) , ejtag (25Mhz), rambist(200Mhz).
  • Role: Top STA for test modes using Tempus for timing closure